This invention relates to a data processing system and more particularly to a data processing system arranged for operating synchronously with a random access memory.
Computer speed is determined by the operating speeds of the data processor, of the memory, of the input/output devices, and of the clock. Individual subsystem operating speeds should be matched with one another to provide the most effective computer operating speed.
During the late 1970's and early 1980's, the microcomputer was in the early stages of development. At that time, a microcomputer system included a microprocessor and a dynamic random access memory. In a microcomputer arrangement, the microprocessor ran synchronously in response to a clock signal, but the dynamic random access memory ran asynchronously with respect to the operation of the microprocessor. The microprocessor clock was applied to a controller circuit that was interposed between the microprocessor and the dynamic random access memory. In response to the microprocessor clock signal, the controller derived other control or clock signals which ran the dynamic random access memory.
As the semiconductor art developed, the operating speeds of microprocessors have become much faster than their associated asynchronous dynamic random access memory. Now microprocessors are capable of completing all of their tasks but then must wait significant periods of time for the dynamic random access memory to complete its tasks.
Recently, designers have proposed arranging computer systems so that both the data processor and the dynamic random access memory operate synchronously in response to a common system clock signal. Operating speeds of such computer systems increase considerably with respect to those using asynchronous random access memory.
Further developments, such as shrinking the dimensions of integrated circuit microprocessors and dynamic random access memories, also have increased computer operating speeds. As a result, data time slots are so short that lead length differences along paths between the microprocessor and different memory arrays are becoming a problem. The different lead lengths cause significantly different time delays for data signals transmitted from the microprocessor to the different memory arrays and from the different memory arrays to the microprocessor.
Because of the very short time slots, the different time delays are substantial with respect to the duration of the time slots. Delay differences of 10%-20% of a time slot may be sufficient to cause errors in signal detection either at the memory arrays or at the microprocessor. A delay difference which exceeds 50% of a time slot places the desired detection time of a data bit outside of its assigned time slot and also causes errors. Such errors create problems which must be resolved for faster data processors to operate effectively.